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Patent Number

US  
First page of patent

Compact proximity display utilizing image transfer


Issued:

2 Aug, 2017

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A compact proximity display system and method that employs an image transfer device is provided. The system and method employs an image transfer device, such as a fiber optic device, which enables remotely locating an image generating source from the display assembly that is mounted on, or proximate to, the helmet bubble, thereby reducing the amount of components located proximate to the helmet bubble. The system and method minimize the intrusion of the entire display system into user's viewing area, and increase safety.


Patent Number

US  
First page of patent

Integrated avionics systems and methods


Issued:

12 Jul, 2017

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Systems and methods are described for synchronizing data in a mobile platform. In one embodiment, a method for synchronizing data in a mobile platform is provided. The method includes: receiving a first synchronization signal at a first remote interface unit from a signal generator; receiving a second synchronization signal at a second remote interface unit from the signal generator; and executing a synchronization state machine of the first and second remote interface units based on the first and second synchronization signals to synchronize outputs of the first and second remote interface units.


Patent Number

US  
First page of patent

Configurable space station momentum


Issued:

7 Dec, 2016

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A method of deploying a modular space station comprises placing an initial space station module in space in a first deployment, the initial space station module including a first control law and momentum component that provides an initial solution for guidance, navigation, and control (GNC) during the first deployment.


Patent Number

US  
First page of patent

Deterministic remote interface unit emulator


Issued:

2 Sep, 2015

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Devices systems and methods are provided for providing a deterministic remote interface unit (RIU) based on a finite state machine. The RIU emulator uses a sequence controller that is configured to receive a synchronization input and to execute a fixed list of unconditional commands in an invariable order of execution based solely upon the synchronization input


Patent Number

US  
First page of patent

Consolidated vehicle propulsion control using integrated modular avionics


Issued:

22 Oct, 2014

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The launch vehicle avionics control system which may include a virtual backplane, a vehicle management computer coupled to the virtual backplane having one or more predetermined schedules, a consolidated propulsion controller coupled to the virtual backplane, at least one engine coupled to the virtual backplane, and at least one control system coupled to the virtual backplane, wherein the vehicle management computer, one or more consolidated propulsion controller, one or more engines and one or more control system are configured to add and consume data from the virtual backplane according to their respective schedules.


Patent Number

US  
First page of patent

Re-configurable multi-purpose digital interface


Issued:

16 Jul, 2014

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Systems and apparatus are provided for a reconfigurable, multi-purpose input/output (I/O) interface comprised of a comparator coupled to a means for signal generation with a switch fabric configured to reconfigure the I/O circuit in real time to perform a variety of signal processing, signal generation and built-in-test functions.


Patent Number

US  
First page of patent

Robotic system with distributed integrated modular avionics across system segments


Issued:

20 Nov, 2013

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A robotic system includes a plurality of robotic elements, each having at least one processing component, at least one memory component, and an I/O interface; and a virtual backplane coupling the plurality of robotic elements.


Patent Number

US  
First page of patent

System and method for a cross channel data link


Issued:

7 Aug, 2013

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A deterministic redundancy management data link consisting of host computers to execute application tasks and to transmit data; a local time-triggered Ethernet switch operable to enforce temporal constraints on time-triggered data; and a time-triggered Ethernet controller coupled to the local time-triggered Ethernet switch and operable to be coupled to a time-triggered Ethernet switch in each of a plurality of other control nodes.


Patent Number

US  
First page of patent

Space telescope system


Issued:

31 Jul, 2013

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A space telescope system including a support platform configured to orbit astronomical object, a plurality of mirrors mounted to the support platform and spaced apart from one another, the plurality of mirrors being configured to reflect a plurality of focused beams, and a focal plane image combiner positioned to intersect the plurality of focused beams and configured to combine the plurality of focused beams to form a composite image.


Patent Number

US  
First page of patent

Universal functionality module


Issued:

6 Mar, 2013

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Methods and apparatus are provided for a Universal functionality Module (UFM) comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for universally interfacing the PLD with any effectuator device. The UFM loads a startup personality bit stream from a boot memory, which allows it to read a pin configuration associated with a effectuator device. The UFM receives a function personality associated with the pin configuration, writes the function personality to programmable logic device, and initiates the function personality.


Patent Number

US  
First page of patent

High integrity data bus fault detection using multiple signal components


Issued:

30 Jan, 2013

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Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.


Patent Number

US  
First page of patent

Cable interface device


Issued:

24 Oct, 2012

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A cable interface device is provided for physically and electronically connecting two devices. The cable interface device comprises a first pin pickup assembly electrically connectable to a first multi-pin connector of a first electronic device having a first pin geometry. The device also includes a hardware specific signal routing adapter connected electronically and physically in series with the pin pickup assembly and a second pin pickup assembly electrically connectable to a second pin connector of a second electronic device having a second pin geometry, the second pin geometry being electronically and mechanically different from the first pin geometry.


Patent Number

US  
First page of patent

Systems and methods for validating predetermined events in reconfigurable control systems


Issued:

9 May, 2012

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Systems and methods for validating predetermined events in reconfigurable control systems are provided. One method includes receiving, by a plurality of redundant processors operating in a first mode, a notice from two of three redundant sensors that the predetermined event occurred and reconfiguring the plurality of redundant processors to operate in a second mode in response to the notice. Another method includes receiving a first notice that one or more sensors detected that a first vehicle is coupled to a second vehicle at a primary control system and a secondary control system and reconfiguring the primary control system and the secondary control system to operate in another mode at substantially the same time in response to the notice.


Patent Number

US  
First page of patent

Reconfigurable virtual backplane systems and methods


Issued:

4 Apr, 2012

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Reconfigurable virtual backplane systems and methods are provided. One virtual backplane system includes a bus, and first and second line cards coupled to the bus. Each line card includes a processor including a memory storing an array of configuration tables. Each configuration table stores a listing of processes to be transmitted to or received from the communication bus, wherein a first configuration table is selected from the first line card upon the occurrence of a first event and a second configuration table is selected from the second line card upon the occurrence of a second event. One method includes connecting first and second buses in first and second systems, respectively, to form a bus for a new system. The method further includes detecting the connection of the first and second buses, and reconfiguring the first and second systems to operate as the new system in response to detecting the connection.


Patent Number

US  
First page of patent

Re-configurable multipurpose analog interface


Issued:

9 Nov, 2011

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Systems and apparatus are provided for interfacing a digital controller with an analog input means. The system comprises a digital controller with the input of the digital controller coupled to the output of the analog-to-digital converter. The system further comprises a digital-to-analog converter coupled to an analog interface circuit. The analog interface circuit comprises a reconfigurable RC network switchably coupled to a first amplifier or to a second amplifier. The analog interface circuit further comprises a third amplifier having an input being coupled to an output of the second amplifier and the output of the third amplifier being coupled to the one or more input signal paths to the first amplifier.


Patent Number

US  
First page of patent

Dual-dual lockstep processor assemblies and modules


Issued:

13 Jul, 2011

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Processor assemblies and modules are provided. One processor assembly includes first and second processors, and first and second input/output (I/O) interfaces coupled to the first and second processors. The first and/or second I/O interfaces are configured to compare outputs of the first and second processors, and render the first and second processors inactive if the outputs are different. One processor module includes first and second buses coupled to first and second processor assemblies. The first processor assembly includes first and second processors coupled to first and second I/O interfaces, wherein the first I/O interface is coupled to the first bus and the second I/O interface is coupled to the second bus. The second processor assembly includes third and fourth processors coupled to third and fourth I/O interfaces, wherein the third I/O interface is coupled to the first bus and the fourth I/O interface is coupled to the second bus.


Patent Number

US  
First page of patent

Celestial body mapping systems and methods


Issued:

18 Aug, 2010

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Systems and methods for mapping a surface of a celestial body containing objects and terrain are provided. One system includes a Synthetic Aperture RADAR (SAR) module configured to capture a high-resolution image of the terrain of at least a portion of the surface and a map module configured to store map data representing the portion of the surface. The system also includes a fusion module configured to combine the high-resolution image and the map data to generate a high-resolution map of the portion of the surface. A method includes orbiting the celestial body, capturing, via the SAR module, a high-resolution image during each orbit, and fusing the captured high-resolution image with a low-resolution map of the surface to generate a high-resolution map of the surface. A computer-readable medium for storing instructions that cause a processor to perform the above method is also provided.


Patent Number

US  
First page of patent

Reconfigurable virtual backplane architecture


Issued:

3 Sep, 2008

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A communication network comprises a communication bus and at least two line cards. Each of the line cards are coupled to the communication bus The line cards comprise a processor and a configuration memory coupled to the processor. The communication occurring on the communication bus is predetermined, but can be reconfigured during real time operation by events or by the addition or subtraction of line cards. The configuration memory comprising an array of configuration tables, each configuration table storing a listing of processes to run and data to be transmitted or received by the process. A current configuration table is selected from the array of configuration tables upon the occurrence of a predefined event.


Patent Number

US  
First page of patent

Protective bus interface and method


Issued:

21 Mar, 2007

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Method and apparatus are provided for preventing faulty commercial-off-the-shelf (COTS) peripherals or I/Os from disabling the bus to which they are connected. The apparatus has isolators coupled to the bus and the I/Os. A controller is coupled between the interfaces, a processor and memory, operating such that an I/O cannot transfer data to the bus without permission from the bus. Isolation memory keeps I/O and bus messages separate. I/O messages are checked before being sent to the bus. The method comprises: determining if there is a message for the peripheral, temporarily storing the message, determining if the message is for output or input, and if for output, sending it to the peripheral, and if for input, requesting and receiving it from the peripheral, temporarily storing and checking it, and transferring it to the bus only if valid. This prevents a failed I/O or peripheral from disabling the bus.


Patent Number

US  
First page of patent

Single board motor controller


Issued:

8 Jan, 2003

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A digital motor controller circuit including a an energy storage device, a bus protection circuit, an input signal selector, a combiner, a calibration device for altering parameters for different applications, a compensator, a motor driver circuit, and feedback circuitry for controlling a motor with a minimum of cost and space requirements.


Patent Number

US  
First page of patent

Low cost high performance single board motor controller


Issued:

25 Apr, 2001

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A motor controller circuit including an energy storage device, a bus protection circuit, an input signal selector, a combiner, a compensator, a modulator, a motor driver circuit, a commutator, a feedback circuitry and a plurality of filters, resistors, inductances, capacitances and optical isolators all contained on a single circuit board for use in controlling a motor with a minimum of cost and space requirements.


Patent Number

US  
First page of patent

Operating system for a multi-tasking operating environment


Issued:

1 May, 1991

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A task scheduler system including an array of priority queues for use in a real time multitasking operating system including equation lists, configuration lists, a function library, input and output drivers, user-created task definition lists of major and minor tasks and interrupt handlers. The system includes task scheduling apparatus which, upon the completion of each library function, interrogates the priority queues and finds the highest priority task segment whose requested resource is available and executed, and which executes task segments in the same priority queue in round-robin fashion. The system further includes task creation apparatus and apparatus for maintaining the status of all major tasks in a system in the states of unlocked and done, unlocked and active, unlocked and waiting, locked and active, or locked and waiting. The status maintaining apparatus also includes apparatus for locking tasks into a mode of operation such that the task scheduler will only allow the locked task to execute and the normal state of priority execution is overridden, and waiting apparatus for suspending operation on a task that requires completion of a library function.